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M66307SP/FP M66307SP/FP
LINE SCAN BUFFER with 16BIT MPU BUS COMPATIBLE INPUTS LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
MITSUBISHI DIGITAL ASSP MITSUBISHI DIGITAL ASSP
DESCRIPTION
The M66307SP/FP is an integrated circuit consisting of a line buffer with static memory, manufactured by the silicon gate CMOS process, which satisfies A3-paper 400DPI requirements. It converts the stored data from the 16-bit MPU bus into serial data and outputs it at a transfer rate of up to 10Mbps synchronously with the external data request clock or an arbitrary continuous clock.
PIN CONFIGURATION (TOP VIEW)
D8 D9 D10 D11
DATA INPUTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC(5V) D7 D6 D5 D4
DATA INPUTS
D12 D13 D14 D15
WRITE CONTROL WR INPUT CHIP SELECT INPUT CS COMMAND/DATA CONTROL INPUT C/D RESET INPUT RESET INTERRUPT REQUEST INTR OUTPUT CLOCK INPUT CLK/ IN CLOCK ENABLE CLKE INPUT
FEATURES
D3 D2 D1 D0
DMA ACKNOWLEDGE INPUT DMA REQUEST DREQ OUTPUT
M66307SP/FP
* * * * * * *
* *
16-bit MPU bus compatible Writing data via DMAC is possible 320-word (5,120-bit) static RAM Data output rate of up to 10Mbps Built-in function to add fixed data of a specified length at the beginning of output data (Fixed data: Continuous High bit or Low bit data) The output format can be selected between FIFO or LIFO. The output method can be selected from two: (1) Synchronized with an arbitrary continuous clock ( IN) on the system side; the frequency of clock output (CLK/ OUT) can be divided by 1, 2, 4, 8, or 16. (2) Synchronized with the data request clock (CLK IN) on the peripheral equipment side. Up to two devices can be cascaded. (1) Toggle configuration (2) 32-bit bus configuration High fan-out outputs (CLK/ OUT, DATA OUT). Io=24mA (4mA for INTR and DREQ 8mA for BUSY/ORDY)
DACK
EXD EXTENDED D INPUT TOG TOGGLE INPUT CLK/ OUT CLOCK
OUTPUT BUSY/ OUTPUT READY OUTPUT
DATA OUT DATA OUTPUT BUSY/ORDY
(0V)GND
Outline 32P4B 32P2W-A
* *
The clock input (CLK/ IN) contains a Schmitt trigger. The reset (RESET), Write (WR) and toggle input (TOG) contain negative noise reduction circuits.
APPLICATION
Image-handling general OA equipment
BLOCK DIAGRAM
WR CS C/D DACK D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 TOG EXD
9 10 11 23 24 25 26 27 28 29 30 31 1 2 16 3 4 5 6 7 8 20 21
GND VCC
16 32
Write control circuit Command registers 16 Data bus buffer
Fixed data length register
Write/send 13 address control 9 circuit
9 4 13 Parallel-serial converter
Output control circuit
22 DREQ
DREQ words register Mode register 320 word CMOS SRAM 16 Expansion control circuit 16 16
Output control circuit
13 INTR 17 BUSY/ORDY
Output control circuit
18 DATA OUT
CLK/ IN 14 CLKE 15 RESET 12
Clock control circuit Reset control circuit
Frequency divider
Clock signal select circuit
Output control circuit
19 CLK/ OUT
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MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
FUNCTION
The M66307 outputs serial data from the system bus to peripheral equipment. Containing an internal 320-word (5,120-bit) line buffer, it can output any number of words(up to 320 words) of stored data from the data bus at a time. The data can be output synchronously with an arbitrary continuous clock ( IN) on the system side or the data request clock (CLK IN) from the peripheral equipment. The data can be output MSB or LSB first, or FIFO (First-in, First-out)
or LIFO (Last-in, First-out) as programmed by the user. When not programmed, the clock and output format are defaulted to CLK IN, MSB and FIFO, respectively. In addition to the above basic functions, the M66307 has such programmable functions that let you add fixed data of a specified length at the beginning of output data, store one line of fixed data using a single substitute command, or repetitively output the data stored in the line buffer.
OPERATION
Interface of the M66307 The M66307 has two interface sections, one on the system bus side and one on the peripheral equipment side as
shown in Figure 1. Up to 320 words of data stored from the system bus side are output to the peripheral equipment after parallel-serial conversion.
Address bus
Control bus Data bus System bus interface section
C/D CS TOG EXD
D0~D15
WR
RESET
IN
DACK DREQ INTR BUSY
CLKE
DATA CLK IN OUT
CLK/ OUT ORDY Peripheral equipment interface section
VCC
Notes : : : : Connect CS to one of address bus directly or via a decoder. Select either CLK IN or IN (indicated by broken line) Connect DACK and DREQ (indicated by broken line) when DMA transfer is used. Make sure the unused active Low inputs are pulled-up to VCC.
Fig. 1 Interface of M66307
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MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
The following describes the operation of the M66307 using the operation flowchart in Fig. 2. The M66307 has three modes: "static mode", "write mode", and "send mode". In the static mode, the M66307 is in a standby state. The M66307 remains in this mode until it is set to the write mode by the operation mode setting command after reset input or until it is set to the write mode after the (operation) stop command is stored. In the write mode, the M66307 stores up to 320 words of data from the 16-bit system bus. In the send mode, the M66307 serially outputs the data stored in the write mode. The write and send modes are set by the operation mode setting command. * Static mode In the static mode, the M66307 is first initialized. This initialization involves selecting IN or CLK IN, setting the divide ratio when IN is selected, and specifying the use of expansion/normal, data store by DMA cycle or MPU cycle, presence of fixed beginning data of specified length added at the beginning of data output, and the polarity (High or Low) of the fixed data. Once the above is programmed, the M66307 executes its functions according to the specification until changed. After the initialization is completed, the M66307 must be programmed for the specification of output formats LSB/ MSB and LIFO/FIFO. In addition, when the "addition of fixed data of specified length at the beginning of data output" is specified in the initialization, the length of the fixed beginning data must be programmed; similarly, when "data store by DMA cycle" is specified, the number of words per line transferred via DMA must be programmed. Once programmed, the specified format is continued until it is changed. The initialization and these settings can only be made in the static mode. When you want to change the specification in the middle of operation, place the M66307 in the static mode using the stop command and reprogram the setting. When initializing the device and setting the output format after rest input, if your setting is the same as the default value, programming may be omitted. (See note 1 in Fig. 4.) When the above settings are completed, the M66307 is ready for data transfer from the system bus to peripheral equipment. * Write mode When settings in the static mode are completed, set to the write mode. In this mode, signals for write to internal memory are enabled, and data is stored in the internal memory at each write cycle executed by the MPU or DMA controller. When storing one line of fixed data, note that once the word length per line is stored as a command, the M66307 operates in the same way as one line of fixed data is stored. In the write mode, data output (DATA OUT) outputs the
polarity of "fixed data" that has been set by initialization. (See Fig. 5.) * Send mode After storing data in the write mode is completed, set to the send mode. In this mode, the M66307 serially outputs the data stored in the write mode according to the setting for the addition of the fixed beginning data and the settings of LSB/MSB and LIFO/FIFO. While the data is output, the M66307 outputs the Busy/Output Ready signal (BUSY/ORDY). When one line length of data is output, BUSY/ORDY is cleared and an interrupt request signal (INTR) is output. For the next line, restart from the setting in the write mode. If you want to output the same data for one line, the same data can be repetitively output without storing by using a transmit repeat request command. When you want to stop the M66307 in the middle of operation or change some settings, use the stop command. The stop command is valid in both write and send modes. When operation is stopped, you can initialize the M66307 and reprogram the output specification, the length of fixed beginning data, and number of DMA transfer words, When you do not reprogram, the same settings before operation is stopped are continued.
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MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Reset C/D=1 Initialization Static mode
C/D=1
Set the number of DREQ words. Set the length of fixed beginning data. Set the output format.
C/D=1
Set to the write mode
C/D=1
Set for operation stop
YES
Fixed data for one line output? NO
Write mode
C/D=1
Set the one line fixed data length.
C/D=0 Storing data from or data bus DACK=0 Storing data for one line length completed? YES C/D=1 Set to send mode (BUSY/ORDY output)
NO
Outputting data
C/D=1 NO Outputting data for one line length completed? YES YES Set for transmit repeat request (INTR output)
Send mode
Repetitive output
NO NO Completed?
Fig. 2 Operation flowchart of M66307
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MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
PIN DESCRIPTIONS
Pin D0~D15 WR CS Name Data inputs Write control input Chip select input DMA acknowledge input Command/ data control input Reset input I/O Input Input Input Normally connected to a 16-bit bus. Data or command is stored to the M66307 at the Low to High transition. This signal is normally connected to the write control signal of the control bus. When Low, this signal allows data or command to be stored from the MPU to the M66307. It is normally connected to the address bus directly or via a decoder. When this signal is High, the MPU cannot access the M66307. When Low, this signal allows data to be stored by DMA transfer. It is normally connected to the DMA acknowledge output (DACK) of the DMA controller.For systems where DMA transfer is not used, this pin must be pulled-up to VCC. This signal discriminates whether the information on the data bus when the MPU accessed the M66307 is command or data. When High, the signal indicates that the information is a command; when Low, it indicates data. It is normally connected to the address bus directly or via a decoder. When Low, this signal initializes the command registers and various circuits of the M66307. As a result, all active Low output signals are set High; clock outputs (CLK, OUT) are set High; data output (DATA OUT) is set Low. This signal requests DMA cycles. When data store by DMA cycle is defined in the initialization and the number of DMA transfer words is specified, this output is set Low when the M66307 is set into the write mode. When the set number of DMA cycles are completed, it returns High. This signal requests an interrupt to the MPU when the written data is sent out (Low output). This request is cleared by MPU access or toggle input(TOG) [when extended toggle is used] (High output). When Low, this signal informs the MPU that no commands other than STOP can be set to the M66307, and informs the peripheral equipment that the M66307 is sending data. When the M66307 is in the send mode, this signal is set Low; when transmission is completed, it returns High. When Low, this signal enables clock input (CLK/ IN); when High, it disables the clock input. When clock input is IN, CLKE is invalid so that this pin must be pulled-up to VCC or pulled-down to GND. CLK IN is generally used as data request clock from peripheral equipment; IN is generally used as continuous clock on the system side. Selection between CLK IN and IN is specified by the initialization command. Select CLK IN when the data output timing must be matched to the timing of the peripheral equipment. Select IN when the timing need not be matched and data can be sent at a stroke using the clock from the system. IN can be divided into one of five smaller frequencies when the peripheral equipment is slow to read data. (Note: The continuous clock of IN may not necessarily be the system clock.) This signal can only be valid when extended toggle is used (using two M66307s) and CLK IN is selected for clock input. This input sets the write and send modes. Each time this signal is set Low, the IC in the write mode is reversed to the send mode and the IC in the send mode is reversed to the write mode. It is impossible to control mode inversion with this function and operation mode setting command together. The data stored in the internal memory or fixed data is serially output synchronously with clock input (CLK/ IN) according to the settings of output format (LSB/MSB, LIFO/FIFO). Peripheral devices take in data with the "rise" of clock pulses. This signal is used for an extended system using two M66307s. Connect the EXD of the master IC to the DATA OUT pin of the slave IC. The EXD of the slave IC must be pulled-up to VCC. (See the application example.) For normal use, pull up EXD to VCC or pull down it to GND. Function
DACK
Input
C/D
Input
RESET
Input
DREQ
DMA request output
Output
INTR BUSY/ ORDY
Output Interrupt request output BUSY/ OUTPUT READY output Clock enable input Clock input Output
CLKE CLK/ IN
Input Input
TOG
Toggle input
Input
DATA OUT CLK/ OUT EXD
Data output
Output
Clock output Extended D input
Output Input
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MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Outline of commands
When the MPU accesses the M66307 for write with C/D = High as shown in Table 1, the M66307 reads the information on the data bus into the register as a command. When the MPU Table 1. Access for Write C/D X X H L X CS X H L L H DACK X H H H L WR H
accesses the M66307 for write with C/D = Low, the M66307 reads the information into the internal memory as data. There are eight kinds of commands classified by the upper four bit (D15 to D12).
Function The M66307 cannot be accessed. Command is stored in the internal command register. Data is stored in the internal memory. (During MPU cycle) (During DMA cycle)
X : denotes H or L.
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MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
1. Register configuration
The M66307 has the command registers shown in Figure 4. The mode register consists of a total of eight flags (F0-F7) and seven bits (B0-B6). Each flag and bit are set to default values (=0) by reset input. There are some commands that do not have a register. These include the one line fixed data setting command, transmit repeat request command, and the stop command.
Group 1 Group 2
Group 3 Group 4
1 2 3 4 5 6 7 8
Initialization command DREQ words setting command Fixed beginning date length setting command Output format setting command Operation mode setting command One line fixed data setting command Transmit repeat request command Stop command
2. Command organization
The commands are broadly classified into four groups as shown in Fig. 3. It shows the relationship between the three modes of the M66307 (static, write and send modes) and the storable commands. Command Mode Static Write Send complete (BUSY="H") Send (BUSY="L") Group 1 Group 2 Group 3 Group 4 5 6 7
Send
Note : Command store is valid within Fig. 3 Command store Map
Description of commands
Command Upper bit name (D15~D12) Initialization command DREQ words setting command Fixed beginning data length setting command Output format setting command Operation mode setting command 1000 Contents This command initializes the hardware setting of the system by selecting clock input and setting the specification for the use of extension, specification for DREQ output, specification for fixed data output, and the logical polarity of "fixed data." When [N] is set, M66307 outputs a Low from the DREQ pin when setting the write mode. When [N+1] words are written by the DMA controller (MPU), it outputs a High from the DREQ pin. This command sets the length of fixed beginning data from 3 to 4,095. When [n] is set to the fixed beginning data length setting register, "fixed data" is output from the DATA OUT pin each time the send mode is entered. When "fixed data" for [n+1] bits is output, the M66307 starts outputting the data stored in memory. Clock output (CLK/ OUT), the clock for synchronization, is output even while fixed data is being output. Note that even when the output format is LIFO, the data in the internal memory is output after outputting fixed data is completed. This command sets the output format for LIFO or FIFO and for MSB first or LSB first. This command is stored in the 4-bit (B3, B2, B1, B0) register shown in Figure 4. The write and send modes are set by this register. The send mode setting command when an extended 32-bit system is used and the mode inverting command when an extended toggle system is used are two-word commands. Store the second word after storing the first word. B3 is a DREQ mask bit. If the write mode is set by setting B3=1 when in the DREQ mode (F4=1), the M66307 does not output a Low from the DREQ pin. When in the DREQ mode, set B3=1 when setting the write mode before storing the one line fixed data setting command. It is impossible to control mode inversion with this command and extended toggle input (TOG) together. When this command is stored, you obtain the same effect as writing "fixed data" for the set number of words. When set to the send mode, "fixed data" equivalent to [(fixed beginning data set value+1)+(one line fixed data setting word value+1)x16] bits is output along with the sync clock (CLK/ OUT). This command allows you to resend the same data that has already been sent. This command becomes executable after transmission is completed. When using an extended system, store the second word of the operation mode setting command following the transmit repeat request command. This command stops the operation of the M66307. This command is valid in all modes. It initializes all registers and circuits except the initialization register, output format setting register, DREQ words setting register, and fixed beginning data length register, thereby placing the M66307 into the static mode. In addition to stopping operation, this command may be used when you want to store the commands that can only be valid in the static mode (e.g., group 1 and group 2 commands).
0111 0110
0100 0000
One line fixed data setting command Transmit repeat request command Stop command
0011
0010
1111
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MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
CLK FLAG Mode register
(1= IN, 0=CLK IN)
Valid when D11=1- Divide retio setting bit (See Table 2). Toggle extension flag(1=toggle; 0=normal use) Invalid when D4=1-32-bit extension flag (1=32; 0=16-bit bus) DREQ mode flag(1=DREQ mode; 0=not DREQ mode) Fixed beginning data output flag (1=output; 0=not output) Fixed data polarity flag (1=High; 0=Low) 0 0 F6 F5 F4 F3 F2
Initialization command 1 0 0 0 F7 B6 B5 B4 0 D15D14D13D12 D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DREQ words register Fixed beginning data length register
DREQ words setting command (valid when F4=1) 0 1 1 1 0 0 0 A8 A7 A6 A5 A4 A3 A2 A1 A0
Number of DMA transfer words
Fixed beginning data length setting command (valid when F3=1) 0 1 1 0 E11E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
Number of fixed beginning data output bits
Mode register
Output format setting command 0 1 0 0 0 0 0 0 0 0 0 0 0 0 F1 F0
LIFO/FIFO flag (1=LIFO; 0=FIFO output) LSB/MSB-first flag (1=LSB; 0=MSB-first output)
One line fixed data setting command 0 0 1 1 0 0 0 W8 W7 W6 W5 W4 W3 W2 W1 W0
One line fixed data output line length
Transmit repeat request command (Note 2) 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Operation mode setting bits (See Table 3.) 0 0 0 0 0 B2 B1 B0
Mode register
Operation mode setting command 0 0 0 0 0 0 0 0
Stop command 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Table 2. Divide Ratio Setting Divide ratio 1 1/2 1/4 1/8 1/16 B6 0 0 0 0 1 B5 0 0 1 1 0 B4 0 1 0 1 0
Table 3. Operation Mode Setting Bit Item Write mode Send mode Write mode Exten- 32 bits 1 First word ded Send mode Second word use 1 First word Toggle Mode inversion Second word Normal use B3 B2 0 0 0 0 0 1 1 B1 0 0 0 0 1 0 1 B0 0 1 0 1 1 0 0
1 : Store the first
2 2
0 0 2 2 0
word, then store the second word. 2 : DREQ mask bit (Refer to description of commands.)
Note 1) The default values of flags (F0-F7) and bits (B0-B6) are zero (0). 2) When using an extended system, store the second word of the operation mode setting command following the transmit repeat request command. 3) It is impossible to control mode inversion with operation mode setting command and extended toggle input (TOG) together. Fig. 4 Register configuration of M66307
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MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Operation timing
1. Storing commands and data from system bus to M66307 Figures 5 and 6 show the timings at which commands and data from the system bus are stored in the M66307 after reset is input or the stop command is issued.
Output format Fixed beginning Write mode set Intialization data length (n) set set CS C/D DACK WR D0~D15 DREQ DATA OUT Static mode
1WORD
(N-1)WORD
NWORD
Fixed data Write mode
Note : Number of transfer words N=1 to 320; fixed data bit length n=3 to 4,096
Fig. 5 Storing commands and data by MPU cycle
Intialization CS C/D DACK WR D0~D15 DREQ DATA OUT
Number of Fixed beginning Output format DREQ words data length (n) set set Write mode set (N-1) set
1WORD
(N-1)WORD
NWORD
Static mode MPU cycle
Fixed data
Write mode DMA cycle
Note : Number of transfer words N=1 to 320; fixed data bit length n=3 to 4,096 Fig. 6 Storing commands by MPU cycle and storing data by DMA cycle
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MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
2. Sending data from M66307 to peripheral equipment After data for one line is stored from the system bus into the M66307, the M66307 serially sends the data to the peripheral equipment. There are 16 methods to send data as shown in Fig. 7. Figures 8 to 11 show the send timings for four of the 16 send method.
Without fixed beginning data output CLK IN With fixed beginning data output Sending method Without fixed beginning data output IN With fixed beginning data output
FIFO LIFO FIFO LIFO FIFO LIFO FIFO LIFO
MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB
Fig. 8 Fig. 11 Fig. 9
Fig. 10
Fig. 7 Various methods for sending data
Send mode set CS C/D DACK WR D0~D15 CLK IN CLK/ OUT DATA OUT Fixed data DOF DOE DOD BUSY/ORDY INTR DREQ Note : DATA OUT outpus fixed data with CLK IN of Nx16+1 or more. : N : Transfer words : Dij : i=transfer words (0-N); j=bits (0-F) Fig. 8 Send timing of M66307 (CLK IN, without fixed beginning data output, FIFO, MSB) DN3 DN2 DN1 DN0 (Note) 1 2 3 Nx16-2 Nx16-1 Nx16 Nx16+1
Write mode set
(Fixed data)
Fixed data
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MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Send mode set CS C/D DACK WR Note : Y=(n+1)+16xN D0~D15 CLK IN CLK/ OUT DATA OUT Fixed data BUSY/ORDY INTR DREQ Note : DATA OUT outputs fixed data with CLK IN of (n+1)+(16xN)+1 or more. : N:Transfer words; n:fixed beginning data length (register set value) : Dij: i=transfer words (0-N); j=bits (0-F) Fig. 9 Send timing of M66307 (CLK IN, with fixed begnning data output, FIFO, MSB) DOF DOE DN3 DN2 DN DN0 (Note) 1 2 n+1 n+2 n+3 n+4 Y-3 Y-2 Y-1 Y (Y+1) (Y+2)
Write mode set
(Fixed data)
Fixed data
Send mode set WR D0~D15 IN CLK/ OUT DATA OUT Fixed data BUSY/ORDY INTR
Note : The same input/output and conditions as in Figure 8 are not shown here. Fig. 10 Send timing of M66307 ( IN without fixed data output, FIFO, MSB)
Write mode set
DOF
DOE
DN3
DN2 DN1
DN0
Fixed data
Send mode set WR D0~D15 1 CLK IN CLK/ OUT DATA OUT Fixed data (Note)
(Fixed
Write mode set
2
3
Nx16-2 Nx16-1 Nx16 Nx16+1
data) Fixed data
FIFO, MSB Output formats FIFO, LSB LIFO, MSB LIFO, LSB
DOF DOO DNF DN0
DOE DO1 DNE DN1
DOD DO2 DND DN2
DN3 DNC D03 DOC
DN2 DND D02 DOD
DN1 DNE D01 DOE
DN0 DNF D00 DOF
Note : The same input/output and conditions as in Figure 8 are not shown here. Fig. 11 Send timing of M66307 (CLK IN, without fixed data output)
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MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO Pd Tstg Supply voltage Input voltage Output voltage Power dissipation Storage temperature Ta=25C Parameter Condition Rating -0.3~+7.0 -0.3~VCC+0.3 0~VCC 700 -65~+150 Unit V V V mW C
RECOMMENDED OPERATING CONDITIONS (Ta=0~70C unless otherwise noted)
Symbol VCC GND VI VO Topr Supply voltage Supply voltage Input voltage Output voltage Ambient temperature 0 0 0 Parameter Min. 4.5 Limits Typ. 5.0 0 VCC VCC 70 Max. 5.5 Unit V V V V C
ELECTRICAL CHARACTERISTICS (Ta=0~70C, VCC=5V10% unless otherwise noted)
Symbol VIH VIL VT+ VT- VH VOH VOL VOH VOL VOH VOL II ICC1 ICC2 CI Input "H" voltage Input "L" voltage Positive threshold voltage Negative threshold voltage Hysteresis width Output "H" voltage Output "L" voltage Output "H" voltage Output "L" voltage Output "H" voltage Output "L" voltage Input current Parameter D0~D15, WR, C/D, CS, DACK, EXD Test condition Min. 2.2 -0.3 2.4 -0.3 0.2 DATA OUT, CLK/ OUT BUSY/ORDY DREQ, INT IOH=-24mA IOL=+24mA IOH=-8mA IOL=+8mA IOH=-4mA IOL=+4mA VI=0~VCC VI=0 or VCC Output pin open VI=0 or VCC Output pin open VCC-0.8 0.55 VCC-0.8 0.55 VCC-0.8 0.55 10 50 110 1 10 Limits Typ. Max. VCC+0.3 0.8 VCC+0.3 0.6 Unit V V V V V V V V V V V A mA mA pF
RESET, CLKE, CLK/ IN, TOG
Supply current (in write and send modes) Supply current (in static mode) Input capacitance
Notes 1 : The current that flows into the IC is defined as positive (unsigned). 2 : The typical values are for VCC=5V and Ta=25C.
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MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
TIMING REQUIREMENTS (Ta=0~70C, VCC=5V10%, GND=0V unless otherwise noted)
Symbol tC(I)/(CI) tW(I)/(CI) tSU(CE-CI) th(CI-CE) tCW tW(W) tSU(D-W) th(W-D) tSU(A-W) th(W-A) tSU(DAC-W) th(W-DAC) trec(W) trec(W-CI) trec(CI-W) tW(R) trec(R-W) tW(T) trec(CI-T) trec(T-CI) trec(W-T) trec(T-W) Parameter Clock cycle time Clock pulse width Clock enable setup time before clock Clock enable hold time after clock Write cycle time Write pulse width Data setup time before rising edge of write signal Data hold time after rising edge of write signal Address setup time before falling edge of write signal Address hold time after rising edge of write signal DMA acknowledge input setup time before falling edge of write signal DMA acknowledge input hold time after rising edge of write signal Write recovery time Clock recovery time after rising edge of write signal Write recovery time after falling edge of clock Reset pulse width Write recovery time after reset Mode inversion pulse width Mode inversion recovery time after falling edge of clock Clock recovery time after rising edge of mode inversion Mode inversion recovery time after rising edge of write signal Write recovery time after rising edge of mode inversion Test condition Min. 100 45 35 5 100 60 45 0 0 0 0 0 40 250 250 250 250 250 100 250 250 250 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note : A delay in clock input (CLK/ IN) rise time (tr) or fall time (tf) may cause erroneous operation. tr, tf : 20ns or less is recommended.
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MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
SWITCHING CHARACTERISTICS (Ta=0~70C, VCC=5V10%)
Symbol tPLH(CI-DO) Propagation time between clock and DATA OUT tPHL(CI-DO) tPLH(CI-CO) tPHL(CI-CO) tPHL(CI-INT) tPLH(CI-BUS) tPLH(I-DO) Propagation time between clock and DATA OUT tPHL(I-DO) tPLH(I-O) Propagation time between clock and CLK/ OUT tPHL(I-O) tPHL(I-INT) tPLH(I-BUS) tPLH(W-DO) Propagation time between write and DATA OUT tPHL(W-DO) tPLH(W-INT) tPHL(W-BUS) tPHL(W-DRE) Propagation time between write and DREQ tPLH(W-DRE) tPLH(T-DO) tPLH(T-INT) tPHL(T-BUS) tPHL(T-DRE) Propagation time between mode inversion and DATA OUT Propagation time between mode inversion and INTR Propagation time between mode inversion and BUSY/ORDY Propagation time between mode inversion and DREQ CL=50pF CL=150pF CL=50pF CL=50pF CL=50pF CL=50pF 20 70 71 68 53 58 85 200 250 200 200 200 ns ns ns ns ns Propagation time between write and INTR Propagation time between clock and INTR Propagation time between clock and INTR Parameter CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF Test condition Min. Limits Typ. 25 27 30 35 21 23 26 31 32 25 35 40 33 36 Max. 75 100 75 100 75 100 75 100 85 85 100 120 100 120 100 120 100 120 100 100 150 180 150 180 150 150 150 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Propagation time between clock and CLK/ OUT
Propagation time between clock and BUSY/ORDY CL=50pF CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF
42 34 39 40 42 47 39 47 51
Propagation time between clock and BUSY/ORDY CL=50pF CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF
Propagation time between write and BUSY/ORDY CL=50pF
Note : AC test waveform Input pulse level Input pulse rise time Input pulse fall time Reference voltage Input voltage Output voltage
0~3V 6ns 6ns 1.3V 1.3V
14
MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
TIMING DIAGRAMS Write Timing
(1) Storing commands and data from MPU
tCW C/D CS tsu(A-W) th(W-A)
tsu(A-W) tW(W)
th(W-A)
WR
D0~D15 tsu(D-W) th(W-D)
(2) Storing data from DMAC
tCW DACK WR tsu(DAC-W) tW(W) th(W-DAC)
D0~D15 tsu(D-W) (3) Write recovery time th(W-D)
WR trec(W)
(4) Output timing during write
Write mode set WR Number of transfer words 1 2 N+1
DREQ tPHL(W-DRE) DATA OUT Fixed data tPHL(W-DO), tPLH(W-DO) tPLH(W-DRE)
Note : The above shows the timing when the DREQ mode flag is set by initialization and the number of transfer words N is set. When the DREQ mode flag is not set, DREQ is tied High.
15
MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Send Timing
(1) Clock input: CLK IN
Send mode WR tC(CI) CLK IN trec(W-CI) tW+(CI) tW-(CI) CLK OUT tPHL(CI-CO) DATA OUT Fixed data tPLH, tPHL(CI-DO) BUSY/ORDY tPHL(W-BUS) INTR tPHL(CI-INT) tPLH(CI-BUS) tPLH(CI-CO) Fixed data trec(CI-W)
Write mode
tPLH(W-INT)
Send mode WR trec(W-CI) tsu(CE-CI) CLKE th(CI-CE) tsu(CE-CI) th(CI-CE)
Write mode
trec(CI-W)
CLK IN
CLK OUT DATA OUT Fixed data Fixed data
(2) Clock input : IN
Send mode WR tC( I) IN tW+( I) OUT tPHL( I- O) DATA OUT Fixed data tPLH,tPHL( I-DO) BUSY/ORDY INTR tPHL(W-BUS) tPLH( I-BUS) tPLH( I- O) Fixed data tW-( I) Write mode
tPHL( I-INT)
tPLH(W-INT)
16
MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Reset Timing
tW(R)
RESET WR
trec(R-W)
Timing when using extended toggle
(1) Write mode setting
tW(T)
TOG
WR tPLH(T-DO), tPHL(T-DO) DATA OUT Fixed data
trec(T-W)
DREQ
tPHL(T-DRE)
INTR
tPLH(T-INT)
(2) Send mode setting
TOG WR CLK IN tW(T)
trec(W-T) trec(T-CI)
BUSY/ORDY
tPHL(T-BUS)
TOG
tW(T) trec(CI-T) th(CI-CE) trec(T-CI) tsu(CE-CI)
CLKE
CLK IN
17
MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
Application Examples 1. Connection diagram
(1) Connection example for memory data transfer by MPU
Control signal
Address bus
Data bus
MPU INT R/W
Image memory and memory management unit
CS
M66307
D0~D15 C/D WR DACK DREQ INTR
VCC N.C.
(2) Connection example for DMA transfer
Decoder
Control signal
Address bus
Data bus
MPU
Image memory and memory management unit
R/W
Decoder
CS
DMAC DACK DREQ R/W
M66307
D0~D15 C/D WR DACK DREQ INTR
18
MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
2. Connection diagram when using extended toggle
(1) Toggle configuration (When using data request clock (CLK IN) on the peripheral equipment side)
DACK RESET C/D CS WR
D0~D15 D8~D15 WR CS
(Slave)
VCC D0~D7 DACK DREQ EXD TOG C/ O DO B/O VCC
D8~D15 WR CS
(Master)
VCC D0~D7 DACK DREQ EXD TOG C/ O DO B/O CLKE CLK IN ORDY CLK/ OUT DATA OUT
C/D RES INTR C/ I CLKE GND
C/D RES INTR C/ I CLKE GND
INTR DREQ
TOG
Fig. 12 Wiring diagram of toggle configuration (2) Toggle configuration (when using continuous clock ( IN) from the system side)
DACK RESET C/D CS WR IN D0~D15 D8~D15 WR CS
(Slave)
M74xx74, one chip
D T
S
Q
D T
S
Q
1/2
2/2
VCC D0~D7 DACK DREQ EXD TOG C/ O DO B/O VCC
D8~D15 WR CS
(Master)
VCC D0~D7 DACK DREQ EXD TOG C/ O DO B/O CLK/ OUT DATA OUT
C/D RES INTR C/ I CLKE GND
C/D RES INTR C/ I CLKE GND
INTR ORDY DREQ TOG
Fig. 13 Wiring diagram of toggle configuration
19
MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
(3) Toggle Operation Flowchart
Reset Master IC Initial setting DREQ words, fixed beginning data length, and output format are set. Toggle input or mode inversion command is set. Data from data bus is stored. Write mode
IC mode Slave IC
Static mode
Static mode
Refer to Common instructions 1, (iv), given below.
Toggle input or mode inversion command is set. Data from data bus is stored, and data is output. Toggle input or mode inversion command is set. Data from data bus is stored, and data is output. Toggle input or mode inversion command is set. Send mode
Write mode
Write mode
Send mode
(4) Toggle Operation Instructions 1 Common instructions (i) Set the operation mode by using mode inversion command or toggle input (TOG). (ii) When setting operation mode with toggle input (TOG) in the DREQ mode (flag F4 = 1), do not use the one-line fixed data setting command. (iii) The settings of master IC and slave IC are determined during the initial setting. When flag F6 is set to 1: M66307 EXD is "H" Slave IC M66307 EXD is "L" Master IC (iv) After a reset and the first mode setting, slave IC is in the send mode. However, transmission is impossible because there is no data in the line memory. New data is written in this stage. (v) It is impossible to control mode inversion by using operation mode setting command and extended toggle input (TOG) together.
2 When CLK IN is used: (i) Toggle operation is feasible when the circuit is connected as shown in Fig. 12. 3 When IN is used: (i) Toggle operation is feasible when the circuit is connected as shown in Fig. 13. (ii) At the initial setting, set clock input to CLK IN. IN cannot be selected. (iii) Divider clock output is not feasible.
20
MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
3.Connection diagram when using extended 32-bit bus
(1) 32-bit bus configuration (when using data request clock (CLK IN) on the peripheral equipment side)
DACK RESET C/D CS WR D16~D31 D0~D15 D8~D15 WR CS
(Slave)
VCC D0~D7 DACK DREQ EXD TOG C/ O DO B/O VCC
D8~D15 WR CS
(Master)
VCC D0~D7 DACK DREQ EXD TOG C/ O DO B/O CLKE CLK IN ORDY CLK/ OUT DATA OUT VCC
C/D RES INTR C/ I CLKE GND INTR DREQ BUSY
C/D RES INTR C/ I CLKE GND
Fig. 14 Wiring diagram of 32-bit bus configuration (2) 32-bit bus configuration (when using continuous clock ( IN) from the system side)
DACK RESET C/D CS WR IN D16~D31 D0~D15 D8~D15 WR CS
(Slave)
M74xx74, one chip
D T
S
Q
D T
S
Q
1/2
2/2
VCC D0~D7 DACK DREQ EXD TOG C/ O DO B/O VCC
D8~D15 WR CS
(Master)
VCC D0~D7 DACK DREQ EXD TOG C/ O DO B/O CLK/ OUT DATA OUT VCC
C/D RES INTR C/ I CLKE GND INTR DREQ BUSY
C/D RES INTR C/ I CLKE GND
ORDY
Fig. 15 Wiring diagram of 32-bit bus configuration
21
MITSUBISHI DIGITAL ASSP
M66307SP/FP
LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS
(3) 32-bit Bus Operation Flowchart
IC mode Master IC Initial setting DREQ words, fixed beginning data length, and output format are set. Slave IC
Reset
Static mode
Static mode
Write mode is set.
Data from data bus is stored.
Write mode
Write mode
Send mode is set.
Data is output to data bus.
Send mode
Send mode
Write mode is set.
Data from data bus is stored.
Write mode
Write mode
Send mode is set.
(4) 32-bit Bus Operation Instructions 1 Common instructions (i) Store the same value for both master IC and slave IC. (ii) The settings of master IC and slave IC are determined during the initial setting. When flag F5 is set to 1: M66307 EXD is "H" Slave IC M66307 EXD is "L" Master IC (iii) The upper 16 bits are sent to the master IC, and the lower 16 bits are sent to the slave IC. The IC that transmits data first is determined by to which of FIFO or LIFO the output setting command is set. When 32-bit parallel data is stored three times, serial output data is transmitted, as shown in the table, according to the output format determined by the output setting command.
2 CLK IN is used: (i) Thirty-two-bit bus operation is feasible when the circuit is connected as shown in Fig. 14. 3 When IN is used: (i) Thirty-two-bit bus operation is feasible when the circuit is used as shown in Fig. 15. (ii) At the initial setting, set clock input to CLK IN. IN cannot be used. (iii) Divider clock output is not feasible. Output format FIFO LIFO LSB LSB Serial output data D0(1)~D31(1), D0(2)~D31(2), D0(3)~D31(3) D0(3)~D31(3), D0(2)~D31(2), D0(1)~D31(1)
MSB D31(1)~D0(1), D31(2)~D0(2), D31(3)~D0(3) MSB D31(3)~D0(3), D31(2)~D0(2), D31(1)~D0(1)
D0(n) and D31(n): 32-bit parallel data stored at the n-th position.
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